Lead SoC Design Engineer - Edge AI, High-Performance ASIC
Listing sourced from adzuna on 8/28/2026. CVCraft does not host this job; clicking Apply redirects to the source.
Job Description
Lead SoC Design Engineer - Edge AI, High-Performance ASIC Job Title: Lead SoC Design Engineer - Edge AI, High-Performance ASIC Job Location: San Francisco, CA or Los Altos, CA - hybrid Compensation: $300K - $400K base DOE plus equity Requirements: SoC Microarchitecture, RTL Design, IP Integration (UCIe, DDR, CPU/GPU/NPU), ARM Cores, Memory Subsystems, AMBA Protocols (CHI, AXI, ACE, APB), HPC / Edge AI SoC Position Overview We're a well-funded, stealth startup building a next-generation, end-to-…
Salary Context for AI Engineer
The US national median for AI Engineer is $185,000; in San Francisco the median is $286,750 (+55% vs national).
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