Senior Manager, Analog & Mixed-Signal Design Engineering
Listing sourced from adzuna on 8/19/2026. CVCraft does not host this job; clicking Apply redirects to the source.
Job Description
The Hard IP and Test Chip Development team within Intel's Central Engineering Group (CEG) is responsible for delivering industry-leading analog and mixed-signal IP for Intel's Client, Data Center, AI, and Foundry businesses. The I/O team develops high-speed serial I/O and die-to-die interconnect solutions across advanced process technologies, enabling next-generation computing platforms. As a Senior Manager, Analog & Mixed-Signal Design Engineering , you will lead a team responsible for develop…
Salary Context for AI Engineer
The US national median for AI Engineer is $185,000; in Phoenix the median is $185,000 (+0% vs national).
Tailor your resume to this role before applying
75% of applicants get filtered by ATS before a human reads them. Run a free 60-second scan to see what keywords are missing from your resume.
Free ATS ScanSimilar Jobs
Mgr, Forward Deployed Engineer, Data & Intelligence
Customer Experience Center (CEZ)
AI Project Manager, Loop Engineer
Director
AI/GenAI Engineer-Senior Manager
Senior React/Next.js Engineer
Pass the ATS Filter Before Applying
Most resumes never reach a human. CVCraft scans your resume against this exact role's keywords in 60 seconds — free.
Scan My Resume Free