Senior Manager, Analog & Mixed-Signal Design Engineering
Listing sourced from adzuna on 8/19/2026. CVCraft does not host this job; clicking Apply redirects to the source.
Job Description
Job Details: Job Description: About the Role The Hard IP and Test Chip Development team within Intel's Central Engineering Group (CEG) is responsible for delivering industry-leading analog and mixed-signal IP for Intel's Client, Data Center, AI, and Foundry businesses. The I/O team develops high-speed serial I/O and die-to-die interconnect solutions across advanced process technologies, enabling next-generation computing platforms. As a Senior Manager, Analog & Mixed-Signal Design Engineering, …
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