ASIC RTL Design Engineer

Responsibilities: Own RTL design for SoC-level blocks or large subsystems from specification to silicon bring-up. Define and implement micro-architecture; write high-quality, synthesizable RTL in SystemVerilog/Verilog. Collaborate with physical design teams on synthesis, timing closure, power and area optimization, DFT hooks, and ECOs. Drive block/subsystem integration and ensure seamless bring-up. Work closely with verification teams to define test plans, assertions (SVA), and coverage goals. …